LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;

ENTITY mux IS
	PORT ( 	a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			sel: IN STD_LOGIC;
			y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END mux ;

ARCHITECTURE mux OF mux IS
BEGIN
	mux: PROCESS (a,b,sel)
	BEGIN	
		IF sel = '1' THEN
			y <=a;
		ELSE
			y <=b;
		END IF;
	END PROCESS;
END mux;